|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
september 2006 hys64d32301hu?[5/6]?c hys[72/64]d64300hu?[5/6]?c hys[64/72]d128320hu?[5/6]?c 184-pin unbuffered double data rate sdram udimm ddr sdram rohs compliant products internet data sheet rev. 1.21
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-08-01 2 03292006-ra8t-mszl hys64d32301hu?[5/6]?c, hys[72/64]d64300hu?[5/6]?c, hys[64/72]d128320hu?[5/6]?c revision history: 2006-09, rev. 1.21 page subjects (major chan ges since last revision) all adapted internet edition previous revision: rev. 1.20, 2005-12 14 changed component configuration for 256mb to 32m x16 26 changed ddr400 t rfc from 70 ns to 65 ns previous revision: rev. 1.10, 2005-05 internet data sheet rev. 1.21, 2006-09 3 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 1overview this chapter gives an overview of the 184-pin unbuffered d ouble data rate sdram product family and describes its main characteristics. 1.1 features ? 184-pin unbuffered double data rate sdram (ecc and non-parity) for pc and workstation main memory applications ? one rank 32m 64, 64m 64, 64m 72 ,and two ranks 128m 64 ,128m 72 organization ? standard double data rate synchronous drams (ddr sdram) single +2.5v ( 0.2v) and +2.6v ( 0.1v) power supply for ddr400 ? built with 512 mbit ddr sdram in p-tsopii-66-1 package ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? ras-lockout supported t rap =t rcd ? all inputs and outputs sstl_2 compatible ? serial presence detect with e 2 prom ? standard mo-206 form factor: 133.35 mm 31.75 mm 4.00 mm max. ? standard reference layout for raw cards: a, b and c ? gold plated contacts ? rohs compliant product 1) table 1 performance 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. part number speed code ?5 ?6 unit speed grade component ddr400b ddr333b ? module pc3200?3033 pc2700?2533 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz internet data sheet rev. 1.21, 2006-09 4 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 1.2 description the hys64d32301hu?[5/6]?c, hys[72/64]d64300hu? [5/6]?c, hys[64/72]d128320hu?[5/6]?c, and are industry standard 184-pin unbuffered double data rate sdram (udimm) organized as 32m 64 (256 mb), 64m 64 (512 mb), 128m 64 (1 gb) for non-parity and 64m 72 (512 mb), 128m 72 (1 gb) for ecc main memory applications. the memory array is designed with 512mbit double data rate synchronous drams. a variety of decoupli ng capacitors are mounted on the printed circuit board. the dimms feature serial presence detect (spd) based on a serial e 2 prom device using the 2- pin i2c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer table 2 ordering information for lead-free products (rohscompliant product) product type 1) 1) all product types end with a place code designating the silicon-die revision. refe rence information available on request. exa mple: hys64d128320hu?5?c, indicating rev.c die are used for sdram components. compliance code 2) 2) the compliance code is printed on the modul e labels and describes the speed sort (for example ?pc3200?), the latencies (for e xample ?30330? means cas latency of 3.0 clocks, ro w-column-delay (rcd) latency of 3 clocks and row precharge latency of 3 clocks), jed ec spd code definition version 0, and t he raw card used for this module. description sdram technology pc3200 (cl=3.0) hys64d32301hu?5?c pc3200u?30331?c3 one rank 256 mb dimm 512 mbit ( 16) hys64d64300hu?5?c pc3200u?30331?a1 one rank 512 mb dimm 512 mbit ( 8) hys72d64300hu?5?c pc3200u?30331?a1 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320hu?5?c pc3200u?30331?b2 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320hu?5?c pc3200u?30331?b2 two ranks 1 gb ecc-dimm 512 mbit ( 8) pc2700 (cl=2.5) hys64d32301hu?6?c pc2700u?25331?c3 one rank 256 mb dimm 512 mbit ( 16) hys64d64300hu?6?c pc2700u?25331?a1 one rank 512 mb dimm 512 mbit ( 8) hys72d64300hu?6?c pc2700u?25331?a1 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320hu?6?c pc2700u?25331?b2 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320hu?6?c pc2700u?25331?b2 two ranks 1 gb ecc-dimm 512 mbit ( 8) internet data sheet rev. 1.21, 2006-09 5 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 2 pin configuration the pin configuration of th e unbuffered ddr sdram dimm is listed by function in table 3 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 4 and table 5 respectively. the pin numbering is depicted in figure 1 . table 3 pin configuration of udimm pin# name pin type buffer type function clock signals 137 ck0 i sstl clock signals 2:0 nc nc ? 16 ck1 i sstl 76 ck2 i sstl 138 ck0 i sstl complement clock signals 2:0 nc nc ? 17 ck1 i sstl 75 ck2 i sstl 21 cke0 i sstl clock enable rank 0 111 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc ? note: 1-rank module control signals 157 s0 i sstl chip select rank 0 158 s1 i sstl chip select rank 1 note: 2-rank module nc nc ? note: 1-rank module 154 ras i sstl row address strobe 65 cas i sstl column address strobe 63 we i sstl write enable address signals 59 ba0 i sstl bank address bus 2:0 52 ba1 i sstl internet data sheet rev. 1.21, 2006-09 6 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 48 a0 i sstl address bus 11:0 43 a1 i sstl 41 a2 i sstl 130 a3 i sstl 37 a4 i sstl 32 a5 i sstl 125 a6 i sstl 29 a7 i sstl 122 a8 i sstl address bus 11:0 27 a9 i sstl 141 a10 i sstl ap i sstl 118 a11 i sstl 115 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 167 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies pin# name pin type buffer type function internet data sheet rev. 1.21, 2006-09 7 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules data signals 2 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 6 dq2 i/o sstl 8 dq3 i/o sstl 94 dq4 i/o sstl 95 dq5 i/o sstl 98 dq6 i/o sstl 99 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 19 dq10 i/o sstl 20 dq11 i/o sstl 105 dq12 i/o sstl 106 dq13 i/o sstl 109 dq14 i/o sstl 110 dq15 i/o sstl 23 dq16 i/o sstl 24 dq17 i/o sstl 28 dq18 i/o sstl 31 dq19 i/o sstl 114 dq20 i/o sstl 117 dq21 i/o sstl pin# name pin type buffer type function internet data sheet rev. 1.21, 2006-09 8 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 121 dq22 i/o sstl data bus 63:0 123 dq23 i/o sstl 33 dq24 i/o sstl 35 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 126 dq28 i/o sstl 127 dq29 i/o sstl 131 dq30 i/o sstl 133 dq31 i/o sstl 53 dq32 i/o sstl 55 dq33 i/o sstl 57 dq34 i/o sstl 60 dq35 i/o sstl 146 dq36 i/o sstl 147 dq37 i/o sstl 150 dq38 i/o sstl 151 dq39 i/o sstl 61 dq40 i/o sstl 64 dq41 i/o sstl 68 dq42 i/o sstl 69 dq43 i/o sstl 153 dq44 i/o sstl 155 dq45 i/o sstl 161 dq46 i/o sstl 162 dq47 i/o sstl 72 dq48 i/o sstl 73 dq49 i/o sstl 79 dq50 i/o sstl 80 dq51 i/o sstl 165 dq52 i/o sstl 166 dq53 i/o sstl 170 dq54 i/o sstl 171 dq55 i/o sstl 83 dq56 i/o sstl 84 dq57 i/o sstl 87 dq58 i/o sstl 88 dq59 i/o sstl 174 dq60 i/o sstl 175 dq61 i/o sstl pin# name pin type buffer type function internet data sheet rev. 1.21, 2006-09 9 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 178 dq62 i/o sstl data bus 63:0 179 dq63 i/o sstl 44 cb0 i/o sstl check bit 0 nc nc ? 45 cb1 i/o sstl check bit 1 nc nc ? 49 cb2 i/o sstl check bit 2 nc nc ? 51 cb3 i/o sstl check bit 3 nc nc ? 134 cb4 i/o sstl check bit 4 nc nc ? 135 cb5 i/o sstl check bit 5 nc nc ? 142 cb6 i/o sstl check bit 6 nc nc ? 144 cb7 i/o sstl check bit 7 nc nc ? 5 dqs0 i/o sstl data strobe bus 7:0 14 dqs1 i/o sstl 25 dqs2 i/o sstl 36 dqs3 i/o sstl 56 dqs4 i/o sstl 67 dqs5 i/o sstl 78 dqs6 i/o sstl 86 dqs7 i/o sstl 47 dqs8 i/o sstl data strobe 8 nc nc ? 97 dm0 i sstl data mask bus 7:0 107 dm1 i sstl 119 dm2 i sstl 129 dm3 i sstl 149 dm4 i sstl 159 dm5 i sstl 169 dm6 i sstl 177 dm7 i sstl 140 dm8 i sstl data mask 8 nc nc ? eeprom 92 scl i cmos serial bus clock pin# name pin type buffer type function internet data sheet rev. 1.21, 2006-09 10 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 91 sda i/o od serial bus data 181 sa0 i cmos slave address select bus 2:0 182 sa1 i cmos 183 sa2 i cmos power supplies 1v ref ai ? i/o reference voltage 184 v ddspd pwr ? eeprom power supply 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v ddq pwr ? i/o driver power supply 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd pwr ? power supply pin# name pin type buffer type function internet data sheet rev. 1.21, 2006-09 11 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss gnd ? ground plane other pins 82 v ddid ood v dd identification 9, 10, 71, 90, 101, 102, 103, 113, 163, 173 nc nc ? not connected pin# name pin type buffer type function internet data sheet rev. 1.21, 2006-09 12 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules table 4 abbreviations for pin type table 5 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or. internet data sheet rev. 1.21, 2006-09 13 03292006-ra8t-mszl hys[64/72]d[16/32/ 128]3xxhu?[5/6]?c unbuffered ddr sdram modules figure 1 pin configuration 184-pin, udimm notes 1. v dd = v ddq , therefore v ddid strap open 2. dq, dqs, dm resistors are 22 ? 5% 3. ban, an, ras , cas , we resistors are 3 ? 5% 0 3 3 ' 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 6 6 ' 4 ' 0 ' 4 1 & |